Instruction Set Architecture (ISA)

ISA Nədir?

ISA (Instruction Set Architecture) - hardware və software arasındaki interface. CPU-nun başa düşdüyü təlimatlar toplusudur.

graph TB
    App[Application] --> OS[Operating System]
    OS --> ISA[Instruction Set Architecture]
    ISA --> Micro[Microarchitecture]
    Micro --> HW[Hardware]
    
    style ISA fill:#ffd700

ISA Komponentləri

• Instructions: Əməliyyat kodları (opcodes)
• Data types: Integer, float, vector
• Registers: Ümumi məqsədli və xüsusi
• Addressing modes: Operandlara müraciət
• Memory model: Byte ordering, alignment
• Exception handling: Interrupt və exception

Əsas ISA Növləri

1. x86 / x86-64

Xüsusiyyətlər:

• CISC arxitekturası
• Variable-length instructions (1-15 bytes)
• Complex addressing modes
• Backward compatibility (1978-dən)
• Dominant desktop/server market

Register Set (x86-64):

• 16 general-purpose registers (RAX, RBX, RCX, ...)
• 64-bit registers
• XMM/YMM/ZMM (SIMD)

Nümunə:

mov rax, 10        ; rax = 10
add rax, rbx       ; rax = rax + rbx
push rax           ; Stack-ə push

2. ARM

Xüsusiyyətlər:

• RISC arxitekturası
• Fixed-length instructions (32-bit və ya 16-bit Thumb)
• Load/Store architecture
• Enerji səmərəli
• Mobile və embedded sistemlər

Register Set (ARM64/AArch64):

• 31 general-purpose registers (X0-X30)
• 64-bit registers
• SIMD və floating-point registers

Nümunə:

mov x0, #10        ; x0 = 10
add x0, x0, x1     ; x0 = x0 + x1
str x0, [sp]       ; Memory-ə write

3. RISC-V

Xüsusiyyətlər:

• Açıq, pulsuz ISA
• Modular və extensible
• Clean, simple design
• 32-bit, 64-bit, 128-bit versiyaları
• Akademik və kommersiya istifadəsi

Register Set:

• 32 integer registers (x0-x31)
• x0 həmişə 0
• Optional floating-point registers

Nümunə:

li x5, 10          ; x5 = 10
add x5, x5, x6     ; x5 = x5 + x6
sw x5, 0(sp)       ; Memory-ə write

ISA Müqayisəsi

Xüsusiyyət	x86-64	ARM	RISC-V
Tip	CISC	RISC	RISC
Instruction length	Variable	Fixed/Variable	Fixed
Registers (GP)	16	31	32
Open-source	❌	❌	✅
Energy efficiency	Orta	Yüksək	Yüksək
Market share	Desktop/Server	Mobile	Yeni
Komplekslik	Yüksək	Orta	Aşağı

Instruction Format

x86-64 Instruction Format (Variable)

graph LR
    I[Instruction] --> P[Prefix 0-4 bytes]
    I --> O[Opcode 1-3 bytes]
    I --> M[ModR/M 0-1 byte]
    I --> S[SIB 0-1 byte]
    I --> D[Displacement 0-4 bytes]
    I --> IM[Immediate 0-4 bytes]

Nümunə:

add rax, rbx  →  48 01 D8 (3 bytes)
add rax, [rbx+8]  →  48 03 43 08 (4 bytes)

ARM Instruction Format (Fixed 32-bit)

graph LR
    I[32-bit Instruction] --> C[Cond 4 bits]
    I --> OP[Opcode 4-8 bits]
    I --> RN[Rn 4 bits]
    I --> RD[Rd 4 bits]
    I --> OP2[Operand2 12 bits]

Nümunə:

ADD R0, R1, R2
31 28 27  25 24  20 19  16 15  12 11       0
Cond  00   ADD    R1     R0     R2

RISC-V Instruction Formats

graph TB
    subgraph "R-type - Register"
        R[funct7 | rs2 | rs1 | funct3 | rd | opcode]
    end
    
    subgraph "I-type - Immediate"
        I[imm12 | rs1 | funct3 | rd | opcode]
    end
    
    subgraph "S-type - Store"
        S[imm7 | rs2 | rs1 | funct3 | imm5 | opcode]
    end

Addressing Modes

Operandlara necə müraciət edilir?

1. Immediate Addressing

Operand instruction-un özündədir.

mov rax, 10        ; rax = 10

graph LR
    I[Instruction] --> V[Value: 10]

2. Register Addressing

Operand register-dədir.

mov rax, rbx       ; rax = rbx

graph LR
    I[Instruction] --> R[Register RBX] --> V[Value]

3. Direct (Absolute) Addressing

Operand memory address-dədir.

mov rax, [0x1000]  ; rax = memory[0x1000]

graph LR
    I[Instruction] --> A[Address: 0x1000]
    A --> M[Memory] --> V[Value]

4. Indirect Addressing

Register memory address-i saxlayır.

mov rax, [rbx]     ; rax = memory[rbx]

graph LR
    I[Instruction] --> R[Register RBX] --> A[Address]
    A --> M[Memory] --> V[Value]

5. Indexed Addressing

Base + Index.

mov rax, [rbx + rcx]   ; rax = memory[rbx + rcx]

graph LR
    I[Instruction] --> B[Base: RBX]
    I --> X[Index: RCX]
    B --> Add[+]
    X --> Add
    Add --> A[Address]
    A --> M[Memory] --> V[Value]

6. Base + Displacement

Base register + offset.

mov rax, [rbx + 8]     ; rax = memory[rbx + 8]

7. Scaled Index

Base + (Index × Scale) + Displacement.

mov rax, [rbx + rcx*4 + 8]   ; Array access

graph LR
    B[Base: RBX] --> Add[+]
    I[Index: RCX] --> Mul[× 4]
    Mul --> Add
    D[Disp: 8] --> Add
    Add --> A[Address] --> M[Memory] --> V[Value]

Register Architecture

x86-64 Registers

graph TB
    subgraph "General Purpose (64-bit)"
        RAX[RAX - Accumulator]
        RBX[RBX - Base]
        RCX[RCX - Counter]
        RDX[RDX - Data]
        RSI[RSI - Source Index]
        RDI[RDI - Destination Index]
        RBP[RBP - Base Pointer]
        RSP[RSP - Stack Pointer]
        R8[R8-R15]
    end
    
    subgraph "Special"
        RIP[RIP - Instruction Pointer]
        RFLAGS[RFLAGS - Status]
    end
    
    subgraph "SIMD"
        XMM[XMM0-XMM15 - 128-bit]
        YMM[YMM0-YMM15 - 256-bit]
        ZMM[ZMM0-ZMM31 - 512-bit]
    end

Register Sizes:

64-bit: RAX, RBX, RCX, ...
32-bit: EAX, EBX, ECX, ... (lower 32 bits)
16-bit: AX, BX, CX, ...     (lower 16 bits)
8-bit:  AL, BL, CL, ...     (lower 8 bits)

ARM64 Registers

graph TB
    subgraph "General Purpose"
        X0[X0-X30 - 64-bit GP registers]
        XZR[XZR/WZR - Zero register]
    end
    
    subgraph "Special"
        SP[SP - Stack Pointer]
        PC[PC - Program Counter]
    end
    
    subgraph "SIMD & FP"
        V[V0-V31 - 128-bit vector]
    end

RISC-V Registers

graph TB
    subgraph "Integer Registers"
        X0[x0/zero - Always 0]
        X1[x1/ra - Return address]
        X2[x2/sp - Stack pointer]
        X3[x3-x31 - General purpose]
    end
    
    subgraph "Floating Point optional"
        F[f0-f31 - FP registers]
    end

Instruction Növləri

1. Data Movement

; x86-64
mov rax, rbx       ; Register to register
mov rax, [rbx]     ; Memory to register
mov [rax], rbx     ; Register to memory
push rax           ; Stack push
pop rbx            ; Stack pop

2. Arithmetic

; x86-64
add rax, rbx       ; Addition
sub rax, rbx       ; Subtraction
imul rax, rbx      ; Multiplication
idiv rcx           ; Division
inc rax            ; Increment
dec rax            ; Decrement

3. Logical

; x86-64
and rax, rbx       ; Bitwise AND
or rax, rbx        ; Bitwise OR
xor rax, rbx       ; Bitwise XOR
not rax            ; Bitwise NOT
shl rax, 2         ; Shift left
shr rax, 2         ; Shift right

4. Control Flow

; x86-64
jmp label          ; Unconditional jump
je label           ; Jump if equal
jne label          ; Jump if not equal
call function      ; Function call
ret                ; Return

5. Comparison

; x86-64
cmp rax, rbx       ; Compare (rax - rbx)
test rax, rax      ; Test (rax & rax)

Assembly Nümunələri

Simple Function (x86-64)

; int add(int a, int b) { return a + b; }
add:
    push rbp           ; Save base pointer
    mov rbp, rsp       ; Set up stack frame
    
    mov eax, edi       ; a (first argument)
    add eax, esi       ; a + b (second argument)
    
    pop rbp            ; Restore base pointer
    ret                ; Return

Loop Example (x86-64)

; int sum_array(int* arr, int n)
sum_array:
    xor eax, eax       ; sum = 0
    xor ecx, ecx       ; i = 0
    
loop_start:
    cmp ecx, esi       ; i < n?
    jge loop_end       ; if not, exit
    
    add eax, [rdi + rcx*4]  ; sum += arr[i]
    inc ecx            ; i++
    jmp loop_start
    
loop_end:
    ret

ARM64 Example

; int add(int a, int b) { return a + b; }
add:
    add w0, w0, w1     ; w0 = w0 + w1
    ret                ; Return

RISC-V Example

; int add(int a, int b) { return a + b; }
add:
    add a0, a0, a1     ; a0 = a0 + a1
    ret                ; Return

Calling Conventions

x86-64 System V ABI (Linux/Unix)

Arguments:

1. RDI
2. RSI
3. RDX
4. RCX
5. R8
6. R9 7+ Stack

Return: RAX

Caller-saved: RAX, RCX, RDX, RSI, RDI, R8-R11 Callee-saved: RBX, RBP, R12-R15

ARM64 AAPCS

Arguments:

1. X0/W0
2. X1/W1
3. X2/W2
4. X3/W3
5. X4/W4
6. X5/W5
7. X6/W6
8. X7/W7

Return: X0

ISA Extensions

x86 SIMD Extensions

graph LR
    Base[x86] --> MMX[MMX - 64-bit]
    MMX --> SSE[SSE - 128-bit]
    SSE --> SSE2[SSE2]
    SSE2 --> SSE3[SSE3]
    SSE3 --> SSE4[SSE4]
    SSE4 --> AVX[AVX - 256-bit]
    AVX --> AVX2[AVX2]
    AVX2 --> AVX512[AVX-512 - 512-bit]

SIMD Example:

; Add 4 floats in parallel
movaps xmm0, [array1]      ; Load 4 floats
movaps xmm1, [array2]      ; Load 4 floats
addps xmm0, xmm1           ; Add 4 floats in one instruction
movaps [result], xmm0      ; Store result

ARM NEON

; Vector addition (ARM NEON)
vld1.32 {q0}, [r0]!        ; Load 4 × 32-bit
vld1.32 {q1}, [r1]!        ; Load 4 × 32-bit
vadd.i32 q0, q0, q1        ; Vector add
vst1.32 {q0}, [r2]!        ; Store result

ISA Design Choices

RISC vs CISC Trade-offs

RISC Üstünlükləri:

• Simple, regular instruction format
• Easier pipelining
• Smaller, faster hardware
• Lower power consumption

CISC Üstünlükləri:

• Richer instruction set
• Smaller code size
• Fewer instructions needed
• Backward compatibility

Modern ISA Trendləri

1. Vector Extensions: SIMD, SVE (ARM), AVX-512
2. Security: ARM TrustZone, Intel SGX
3. Virtualization: Hardware-assisted virtualization
4. Atomic operations: Lock-free programming
5. Custom extensions: Domain-specific accelerators

Praktiki Nümunə: High-Level to Assembly

C Code:

int factorial(int n) {
    if (n <= 1) return 1;
    return n * factorial(n - 1);
}

x86-64 Assembly:

factorial:
    cmp edi, 1         ; n <= 1?
    jg .recurse        ; if not, recurse
    mov eax, 1         ; return 1
    ret
    
.recurse:
    push rdi           ; Save n
    dec edi            ; n - 1
    call factorial     ; factorial(n-1)
    pop rdi            ; Restore n
    imul eax, edi      ; n * factorial(n-1)
    ret

Əlaqəli Mövzular

• CPU Architecture: ISA-nın hardware-də implementasiyası
• Compiler Design: High-level code-dan ISA-ya tərcümə
• Performance: ISA seçiminin performansa təsiri
• Cross-platform Development: Müxtəlif ISA-lar üçün kod yazma